In the last 40 years, the systematic downscaling of CMOS Integrated Circuit (IC) technologies has enabled unprecedented improvements in the transistor density, frequency of operation, energy efficiency and reliability. Most recent CMOS technologies allow the integration of several billions of transistors in a digital microprocessor chip the size of a fingernail. While technology downscaling has been extremely beneficial for digital circuits, the design of analog frontend electronics and Analog-to-Digital Converters (ADCs) in deep sub-micron CMOS technologies is becoming increasingly challenging due to the systematic power supply reduction, the intrinsically larger device parameter variability, and the higher low-frequency noise level of these transistors. To achieve high performance while ensuring a high level of reliability, complex and accurate calibration circuits need to be added to the ICs to counteract these effects. However, the design of these calibration circuits is challenging, and their effectiveness is typically limited to specific operating conditions.   

This project is done in cooperation with NXP semiconductors, Eindhoven.

Your duties

As a PhD researcher from the Integrated Circuits group, you will investigate a novel methodology to design and implement calibration techniques for Analog-to-Digital Converters with the aid of Machine Learning (ML). During your PhD you will first identify the root causes which limit ADC performance. Next you will investigate suitable ML algorithms to correct these errors, calibrate the ADC behavior and improve its performance. Finally, you will design a novel ADC with embedded ML calibration circuits, achieving beyond state-of-the-art performance.

In summary your main tasks will be:

• Analyze and identify the major root causes which limit the performance of specific state-of-the-art ADCs.
• Explore new design methodologies to post-correct errors in ADCs and enable smart calibrations using Machine Learning.
• Investigate methods to efficiently train the ML algorithms using a reduced set of data points.
• Demonstrate the potential and effectiveness of the proposed approach by designing, implementing and characterizing Analog-to-Digital Converters achieving a performance beyond current state-of-the-art.
• Dissemination of the results of your research in international and peer-reviewed journals and conferences.  
• Get involved in educational tasks such as the supervision of Master/Bachelor students and internships.
• Writing a dissertation based on the research outcomes and successfully defending it. 

We are looking for a candidate who meets the following requirements:

• You have a strong background in mixed-signal Integrated Circuit (IC) design.
• You have a solid understanding of Analog-to-Digital Converters.
• You hold an MSc degree in Electrical Engineering.
• You are a talented and enthusiastic young researcher.
• Prior knowledge of machine learning algorithms, neural and/or Bayesian networks is a plus.
• You have good programming skills (preferably Python or MATLAB).
• You have good communication skills and can work in a multidisciplinary team.

You will need to have a good proficiency in spoken and written English; knowledge of Dutch is not required.

• A meaningful job in a dynamic and ambitious university with the possibility to present your work at international conferences.
• A full-time employment for four years, with an intermediate evaluation (go/no-go) after nine months.
• To develop your teaching skills, you will spend up to 10% of your employment on teaching tasks.
• To support you during your PhD and to prepare you for the rest of your career, you will make a Training and Supervision plan and you will have free access to a personal development program for PhD students. 
• High-quality training programs and other support to grow into a self-aware, autonomous scientific researcher. At TU/e we challenge you to take charge of your own learning process.
• A gross monthly salary and benefits (such as a pension scheme, pregnancy and maternity leave, partially paid parental leave) in accordance with the Collective Labor Agreement for Dutch Universities.
• Additionally, an annual holiday allowance of 8% of the yearly salary, plus a year-end allowance of 8.3% of the annual salary.
• Should you come from abroad and comply with certain conditions, you can make use of the so-called '30% facility', which permits you not to pay tax on 30% of your salary.
• A broad package of fringe benefits, including an excellent technical infrastructure, moving expenses, and savings schemes.
• Family-friendly initiatives are in place, such as an international spouse program, and excellent on-campus children day care and sports facilities.
• A Staff Immigration Team and a tax compensation scheme (the 30% facility) for international candidates.