PhD in Analog-to-Digital Converter Design driven by Learning

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PhD in Analog-to-Digital Converter Design driven by Learning

Deadline Published on Vacancy ID 2025/135
Apply now
16 days remaining

Academic fields

Engineering

Job types

PhD

Education level

University graduate

Weekly hours

40 hours per week

Salary indication

€2901—€3707 per month

Location

De Zaale, 5612AZ, Eindhoven

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Job description

In the last 40 years, the systematic downscaling of CMOS Integrated Circuit (IC) technologies has enabled unprecedented improvements in transistor density, frequency of operation, energy efficiency, and reliability. Most recent CMOS technologies allow the integration of several billions of transistors in a digital microprocessor chip the size of a fingernail. While technology downscaling has been extremely beneficial for digital circuits, the design of analog frontend electronics and Analog-to-Digital Converters (ADCs) in deep sub-micron CMOS technologies is becoming increasingly challenging due to the systematic power supply reduction, the intrinsically larger device parameter variability, and the higher low-frequency noise level of these transistors. Thus to counteract these effects and design high-performance ADCs operating with a high level of reliability, complex and accurate calibration circuits need to be added. However, the design of these calibration circuits is challenging, and their effectiveness is typically limited to specific operating conditions.

This project is done in cooperation with NXP Semiconductors, Eindhoven.

Your Duties As a PhD researcher from the Integrated Circuits group, you will investigate novel methodologies to design Analog-to-Digital Converters (including pipelined, Successive-Approximation (SAR), and Sigma Delta architectures) and calibrate them using Machine Learning (ML) techniques. During your PhD, you will first identify the root causes that limit the ADC performance, and then you will implement solutions to correct these errors, calibrate the ADC behavior, and improve its performance. Finally, you will design a novel ADC that includes the ML calibration and the required peripheral circuits, achieving beyond state-of-the-art performance.

In summary, your main tasks will be:
  • Analyze and identify the major root causes limiting the performance of the specific ADC architecture.
  • Design and implementation (at transistor-level) of the calibration schemes to mitigate non-idealities in ADCs;
  • Demonstrate the potential and effectiveness of the proposed approach by designing, implementing, and characterizing Analog-to-Digital Converters achieving a performance beyond current state-of-the-art;
  • Dissemination of the results of your research in international and peer-reviewed journals and conferences;
  • Get involved in educational tasks such as the supervision of Master/Bachelor students and internships;
  • Writing a dissertation based on the research outcomes and successfully defending it.

Requirements

We are looking for a candidate who meets the following requirements:
  • You have a strong background in mixed-signal Integrated Circuit (IC) design.
  • You have a solid understanding of Analog-to-Digital Converters.
  • You hold an MSc degree in Electrical Engineering.
  • You are a talented and enthusiastic young researcher.
  • Prior knowledge of machine learning and neural networks is a plus.
  • You have good programming skills (preferably Python or MATLAB).
  • You have good communication and presentation skills and can work in a multidisciplinary team.

You will need to have a good proficiency in spoken and written English; knowledge of Dutch is not required.

Conditions of employment

Fixed-term contract: 4 years.

  • A meaningful job in a dynamic and ambitious university, in an interdisciplinary setting and within an international network. You will work on a beautiful, green campus within walking distance of the central train station. In addition, we offer you:
  • Full-time employment for four years, with an intermediate assessment after nine months. You will spend a minimum of 10% of your four-year employment on teaching tasks, with a maximum of 15% per year of your employment.
  • Salary and benefits (such as a pension scheme, paid pregnancy and maternity leave, partially paid parental leave) in accordance with the Collective Labour Agreement for Dutch Universities, scale P (min. € 2,901 max. € 3,707).
  • A year-end bonus of 8.3% and annual vacation pay of 8%.
  • High-quality training programs and other support to grow into a self-aware, autonomous scientific researcher. At TU/e we challenge you to take charge of your own learning process.
  • An excellent technical infrastructure, on-campus children's day care and sports facilities.
  • An allowance for commuting, working from home and internet costs.
  • A Staff Immigration Team and a tax compensation scheme (the 30% facility) for international candidates.

Additional information

Do you recognize yourself in this profile and would you like to know more? Please contact the hiring manager dr.ir. Marco Fattori, M.Fattori@tue.nl or dr.ir. Pieter Harpe, P.J.A.Harpe@tue.nl.

Visit our website for more information about the application process or the conditions of employment.

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